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| ? 2005-2014 microchip technology inc. ds20002018h-page 1 mcp2021/2/1p/2p features: the mcp2021/2/1p/2p are compliant with lin bus specifications 1.3, 2.1 and are compliant to sae j2602-2 support baud rates up to 20 kbaud ? with lin-compatible output driver 43v load dump protected very low emi meets stringent oem requirements wide supply voltage, 6.0v-18.0v continuous: - maximum input voltage of 30v extended temperature range: -40 to +125c interface to pic ? eusart and standard usarts local interconnect network (lin) bus pin: - internal pull-up resistor and diode - protected against ground shorts - protected against loss of ground - high-current drive automatic thermal shutdown on-chip voltage regulator: - output voltage of 5.0v with tolerances of 3% overtemperature range - available with alternate output voltage of 3.3v with tolerances of 3% overtemperature range - maximum continuous input voltage of 30v - internal thermal overload protection - internal short circuit current limit - external components limited to filter capacitor and load capacitor two low-power modes: - receiver on, transmitter off, voltage regulator on ( ? 85 a) - receiver monitoring bus, transmitter off, voltage regulator off ( ? 16 a) description: the mcp2021/2/1p/2p provides a bidirectional, half- duplex communication physical interface to automotive and industrial lin systems that meets the lin bus specification revision 2.1 and sae j2602-2. the devices incorporate a voltage regulator with 5v at 50 ma or 3.3v at 50 ma regulated power-supply outputs. the regulator is short-circuit protected, and is protected by an internal thermal shutdown circuit. the device has been specifically designed to operate in the automotive operating environment and will survive all specified transient conditions while meeting all of the stringent quiescent current requirements. the mcp2021/2/1p/2p family of devices includes the following packages. 8-pin pdip, dfn and soic packages: mcp2021-330, lin-compatible driver, 8-pin, 3.3v regulator, wake up on dominant level of l bus mcp2021-500, lin-compatible driver, 8-pin, 5.0v regulator, wake up on dominant level of l bus mcp2021p-330, lin-compatible driver, 8-pin, 3.3v regulator, wake up at falling edge of l bus voltage mcp2021p-500, lin-compatible driver, 8-pin, 5.0v regulator, wake up at falling edge of l bus voltage 14-pin pdip, tssop and soic packages with reset output: mcp2022-330, lin-compatible driver, 14-pin, 3.3v regulator, reset output, wake up on dominant level of l bus mcp2022-500, lin-compatible driver, 14-pin, 5.0v regulator, reset output, wake up on dominant level of l bus mcp2022p-330, lin-compatible driver, 14-pin, 3.3v regulator, reset output, wake up at falling edge of lbus voltage mcp2022p-500, lin-compatible driver, 14-pin, 5.0v regulator, reset output, wake up at falling edge of l bus voltage lin transceiver with voltage regulator downloaded from: http:///
mcp2021/2/1p/2p ds20002018h-page 2 ? 2005-2014 microchip technology inc. package types mcp2021/2 block diagram 12 3 4 87 6 5 12 3 4 1413 12 11 10 98 56 7 r xd cs/lwake v reg t xd fault /t xe v bb l bus v ss r xd cs/lwake v reg t xd reset ncnc fault /t xe v bb l bus v ss ncnc nc mcp2021, mcp2021p 4x4 dfn* 1 2 3 4 8 7 6 5 ep 9 mcp2021, mcp2021p pdip, soic mcp2022, mcp2022p pdip, soic, tssop r xd cs/lwake v reg t xd fault /t xe v bb l bus v ss * includes exposed thermal pad (ep); see table 1-2 . 1 2 3 4 8 7 6 5 ep 9 r xd cs/lwake v reg t xd fault /t xe v bb l bus v ss mcp2021, 6x5 dfn-s* voltage regulator ratiometric reference oc thermal protection internal circuits v reg fault /t xe r xd t xd v bb l bus v ss ~30 k ? cs/lwake wake-up logic and power control reset short circuit protection short circuit protection thermal protection ( mcp2022 only ) C+ downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 3 mcp2021/2/1p/2p mcp2021p/2p block diagram ratiometric reference internal circuits v reg r xd t xd v bb v ss ~30 wake-up logic and power control reset thermal protection k ? ( mcp2022p only ) l bus short-circuit protection oc cs/lwake fault /t xe C + voltage regulator short-circuit protection thermal short-circuit protection and downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 4 ? 2005-2014 microchip technology inc. notes: downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 5 mcp2021/2/1p/2p 1.0 device overview the mcp2021/2/1p/2p provides a physical interface between a microcontroller and a lin half-duplex bus. it is intended for automotive and industrial applications with serial bus speeds up to 20 kbaud. the mcp2021/2/1p/2p provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. this device will translate the cmos/ttl logic levels to lin-level logic, and vice versa. the lin specification 2.0 requires that the transceiver(s) of all nodes in the system be connected via the lin pin, referenced to ground, and with a maximum external termination resistance load of 510 ? from lin bus to battery supply. the 510 ? ? corresponds to one master and sixteen slave nodes. the mcp2021/2/1p/2p-500 provides a +5v, 50 ma, regulated power output. the regulator uses an ldo design, is short-circuit protected, and will turn the regulator output off if it falls below 3.5v. the mcp2021/2/1p/2p also includes thermal-shutdown protection. the regulator is specifically designed to operate in the automotive environment and will survive +43v load dump transients, double-battery jumps, and reverse battery connections when a reverse blocking diode is used. the other members of the mcp2021/2/1p/2p-330 family output +3.3v at 50 ma with a turn-off voltage of 2.5v. (see section 1.6 ?internal voltage regulator? ). mcp2021/2 wakes from power-down mode on a dominant level on l bus . mcp2021p/2p wakes at a transition from recessive level to dominant level on lbus. 1.1 optional external protection 1.1.1 reverse battery protection an external reverse-battery-blocking diode should be used to provide polarity protection (see figure 1-6 ). 1.1.2 transient voltage protection (load dump) an external 43v transient suppressor (tvs) diode, between v bb and ground, with a 50 ? transient protec- tion resistor (r tp ) in series with the battery supply and the v bb pin, protect the device from power transients (see figure 1-6 ) and esd events. while this protection is optional, it is considered good engineering practice. the resistor value is chosen according to equation 1-1 . equation 1-1: 1.2 internal protection 1.2.1 esd protection for component-level esd ratings, please refer to the section 2.1 ?absolute maximum ratings?? . 1.2.2 ground loss protection the lin bus specification states that the lin pin must transition to the recessive state when ground is disconnected. therefore, a loss of ground effectively forces the lin line to a high-impedance level. 1.2.3 thermal protection the thermal protection circuit monitors the die tem- perature and is able to shut down the lin transmitter and voltage regulator if it detects a thermal overload. there are three causes for a thermal overload. a thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions: voltage regulator overload lin bus output overload increase in die temperature due to increase in environmental temperature driving the t xd and checking the r xd pin makes it pos- sible to determine whether there is a bus contention (i.e., r xd = low, t xd = high) or a thermal overload con- dition (i.e., r xd = high, t xd = low). r tp ? (v bb min - 5.5) / 250 ma. 5.5v = v uvlo + 1.0v, 250 ma is the peak current at power-on when v bb = 5.5v downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 6 ? 2005-2014 microchip technology inc. figure 1-1: thermal shutdown state diagrams 1.3 modes of operation for an overview of all operational modes, please refer to tab le 1 -1 . 1.3.1 power-on reset mode upon application of v bb , the device enters power-on reset mode (por). during this mode, the part main- tains the digital section in a reset mode and waits until the voltage on pin v bb rises above the on threshold (typically 5.75v) to enter to the ready mode. if during the operation, the voltage on pin v bb falls below the off threshold (typically 4.25v), the part comes back to the por mode. 1.3.2 power-down mode in power-down mode, the transmitter and the voltage regulator are off. only the receiver wake-up from the lin bus section, and the cs/lwake pin wake-up circuits, are in operation. this is the lowest power mode. if pin cs/lwake goes to a high level during power-down mode, the device immediately enters ready mode and enables the voltage regulator; and after the output has stabilized (approximately 0.3 ms to 1.2 ms), the device goes to operation mode or trans- mitter-off mode (see figure 1-2 for mcp2021/2 and figure 1-4 for mcp2021p/2p). lin bus activity will also change the device from power-down mode to ready mode. mcp2021/2 wakes up on the dominant level of the lin bus, and mcp2021p/2p on a falling edge that follows a domi- nant level lasting 20 s of time. the power-down mode can be reached through either operation mode or transmitter-off mode. 1.3.3 ready mode upon entering ready mode, the voltage regulator and receiver-threshold-detect circuit are powered up. the transmitter remains in an off state. the device is ready to receive data as soon as the regulator is stabi- lized, but not to transmit. if a microcontroller is being driven by the voltage regulator output, it will go through a por and initialization sequence. the lin pin is in the recessive state for mcp2021/2 and in floating state for mcp2021p/2p. the device will stay in ready mode until the output of the voltage regulator has stabilized and the cs/lwake pin is true ( 1 ). after v reg is stable and cs/lwake is high, mcp2021/2 will enter operation mode; and mcp2021p/2p will enter either operation mode or transmitter-off mode, depending on the level of the fault /t xe pin (refer to figure 1-4 ). 1.3.4 operation mode in this mode, all internal modules are operational. the device will go into the power-down mode on the falling edge of cs/lwake. for the mcp2021p/2p devices, the pull-up resistor is switched on only in this mode. operation mode transmitter shutdown l bus voltage shutdown regulator output temperature mcp2021/2/1p/2p ds20002018h-page 8 ? 2005-2014 microchip technology inc. figure 1-2: mcp2021/2 operat ional modes state diagram figure 1-3: mcp2021p/2p op erational modes diagrams power-down tx: off rx: off v reg :off cs/lwake = 0 transmitter off tx: off rx: on v reg :on por tx: off rx: off v reg :off operation tx: on rx: on v reg :on ready tx: off rx: on v reg :on v bat > 5 . 75 v cs/lwake = & vreg_ok = cs/lwake = 0 fault/t xe = 0 or faults* fault/t xe = &no faults* cs/lwake = or dominant level on l bus start *fault: thermal shutdown and t xd /l bus permanent dominant note: while the device is in shutdown, t xd should not be actively driven high or it may power internal logic through the esd diodes and may damage the device. power-down tx: off rx: off v reg :off cs/lwake = 0 transmitter off tx: off rx: on v reg :on por tx: off rx: off v reg :off operation tx: on rx: on v reg :on ready tx: off rx: on v reg :on v bat > 5 . 75 v cs/lwake = & v reg _ok = & fault/t xe = cs/lwake = 0 fault/t xe = 0 or faults* fault/t xe = &no faults* cs/lwake = or falling edge on l bus start *fault: thermal shutdown and t xd /l bus permanent dominant cs = & v reg _ok = &fault/t xe = 0 downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 9 mcp2021/2/1p/2p figure 1-4: mcp2021p/2p wake-up due to bus disconnecting ready state sleep 0 l bus fault t xe v reg cs lwake 0 downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 10 ? 2005-2014 microchip technology inc. figure 1-5: forced power-down mode sequence for mcp2021p/2p cs/lwake v reg fault/t xe l bus operation mode transmitter-off mode power-down mode t csactive > = 2 v fault/t xe = forced internally fault/t xe = 0 forced externally l bus disconnected; e.g., master pull-up &internal resistor off; l bus floating. forced power-down mode after bus-off instruction or a longer lin-bus inactivity ( > = 4 sec according to lin specification) state downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 11 mcp2021/2/1p/2p table 1-1: overview of operational modes state transmitter receiver voltage regulator operation comments por off off off read v bb ; if v bb > 5.75v, proceed to ready mode ready off on on mcp2021/2 : if cs/lwake is high level, then proceed to operation mode. mcp2021p/2p : if cs/lwake is high level and fault /t xe is high level, then proceed to operation mode. if cs/lwake is high level and fault /t xe is low level, then proceed to txoff mode. bus off state operation on on on if cs/lwake is low level, then proceed to power-down mode. if fault /t xe is low level or t xd /l bus permanent dominant is detected, then proceed to transmitter-off mode. normal operation mode power-down off activity detect off on lin bus falling, go to ready mode. on cs/lwake high level, go through ready mode; then, to either operation or transmitter-off mode (refer to figure 1-2 and figure 1-3 ). low-power mode transmitter-off off on on if cs/lwake is low level, then proceed to power-down mode. if fault /t xe is high, then proceed to operation mode. downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 12 ? 2005-2014 microchip technology inc. 1.4 pin descriptions 1.4.1 receive data output (r xd ) the receive data output pin is a standard cmos output and follows the state of the lin pin. 1.4.2 chip select pin (cs/lwake) an internal pull-down resistor will keep the cs/lwake pin low. this is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a por and i/o initialization sequence. the pin must see a high level to activate the transmitter. if cs/lwake = 0 when the v bb supply is turned on, the device stays in ready mode (low-power mode). in ready mode, both the receiver and the voltage regulator are on and the lin transmitter driver is off. if cs/lwake = 1 when the v bb supply is turned on, the device will proceed to either operation or transmit- ter-off mode (refer to figure 1-2 and figure 1-3 ) after the v reg output has stabilized. this pin may also be used as a local wake-up input (see figure 1-6 ). in this implementation, the microcon- troller will set the i/o pin that controls the cs/lwake as an high-impedance input. the internal pull-down resistor will keep the input low. an external switch, or other source, can then wake up the transceiver and the microcontroller. 1.4.3 power output (v reg ) positive supply voltage regulator output pin. 1.4.4 transmit data input (t xd ) the transmit data input pin has an internal pull-up to v reg . the lin pin is low (dominant) when t xd is low, and high (recessive) when t xd is high. for extra bus security, t xd is internally forced to 1 when v reg is less than 1.8v (typical). if the thermal protection detects an overtemperature condition while the signal t xd is low, the transmitter is shut down. the recovery from the thermal shutdown is equal to adequate cooling time. 1.4.5 ground pin (v ss ) ground pin. 1.4.6 lin bus pin (l bus ) the bidirectional lin bus interface pin is the driver unit for the lin pin and is controlled by the signal t xd . lin has an open collector output with a current limitation. to reduce emi, the edges during the signal changes are slope-controlled. to further reduce radiated emis- sions, the l bus pin has corner-rounding control for both falling and rising edges. the internal lin receiver observes the activities on the lin bus, and generates output signal r xd that follows the state of the l bus . a 1 st degree with 1 s time constant (160 khz), low-pass input filter is placed to maintain emi immunity. 1.4.7 no connection (nc) no internal connection. table 1-2: pinout descriptions pin name devices pin type function 8-pin pdip, soic 4x4 dfn 6x5 dfn-s 14-pin pdip, soic, tssop normal operation r xd 1 1 1 o receive data output (cmos) cs/lwake 2 2 2 ttl chip select (ttl) v reg 33 3o p o w e r o u t p u t t xd 4 4 4 i transmit data input (ttl) v ss 5 5 11 p ground l bus 6 6 12 i/o lin bus (bidirectional) nc 6 C 10 no connection v bb 7 7 13 p battery supply fault /t xe 8 8 14 od fault detect output, transmitter enable (od) reset 5 od reset signal output (od) ep 9 exposed thermal pad legend: o = output, p = power, i = input, ttl = ttl input buffer, od = open-drain output note: cs/lwake should not be tied directly to v reg as this could force the mcp202x into operation mode before the microcontroller is initialized. downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 13 mcp2021/2/1p/2p 1.4.8 battery positive supply voltage (v bb ) battery positive supply voltage pin. this pin is also the input for the internal voltage regulator. 1.4.9 f ault /t xe fault detect output and transmitter enable input bidirectional pin. this pin is an open-drain output. its state is defined as shown in table 1-3 . the transmitter driver is disabled whenever this pin is low ( 0 ), either from an internal fault condition or by external drive. this allows the transmitter to be placed in an off state and still allow the voltage regulator to operate. refer to ta bl e 1 - 1 . the fault /t xe also signals a mismatch between the t xd input and the l bus level. this can be used to detect a bus contention. since the bus exhibits a propagation delay, the sampling of the internal compare is debounced to eliminate false faults. this pin has an internal pull-up resistor of approximately 750 k ? . the internal pull-up resistor may be too weak for some applications. we recom- mend adding a 10 kohm external pull-up resistor to ensure a logic high level. the fault /t xe pin sampled at a rate faster than every 10 s. 1.4.10 reset reset is an open-drain output pin. this pin reflects an internal signal that tracks the internal system voltage has reached a valid, stable level. as long as the internal voltage is valid, this pin will keep high-impedance. when the system voltage drops below the minimum required, the voltage regulator will shut down and immediately convert the reset output to short to gnd. a pull-up resistor is needed to change the output to high/low voltage. when connected to a microcontroller input, this can provide a warning that the voltage regulator is shutting down (see figure 1-2 ). alternately, it can act as an external brown-out by connecting the reset output to mclr (see figure 1-2 ). in addition to monitoring the internal voltage, reset is asserted immediately upon entering the power-down mode. 1.4.11 exposed thermal pad (ep) it is recommended to connect this pad to v ss to enhance electromagnetic immunity and thermal resistance. note 1: the fault /t xe pin is true ( 0 ) whenever the internal circuits have detected a short or thermal excursion and have disabled the l bus output driver. 2: fault /t xe is true ( 0 ) when v reg not ok and has disabled the l bus output driver. table 1-3: fault/ txe truth table t xd in r xd out lin bus i/o thermal override fault/ t xe definition external input driven output lhv bb off h l fault , t xd driven low, l bus shorted to v bb ( note 1 ) hh v bb off h h ok llg n d o f f h h ok hlg n d o f f h h ok , data is being received from the l bus xxv bb on h l fault , transceiver in thermal shutdown xxv bb xlx no fault , the cpu is commanding the transceiver to turn off the transmitter driver legend: x = dont care note 1: the fault /t xe is valid after approximately 25 s after t xd falling edge. this is to eliminate false fault reporting during bus propagation delays. downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 14 ? 2005-2014 microchip technology inc. 1.5 typical applications figure 1-6: typical mcp2021/mcp2021p application lin bus v bb l bus v reg t xd rxd v ss v dd txd r xd +12 c bat c reg cs/lwake i/o fault/ t xe i/o 43v ( 5 ) 1k ? +12 master node only +12 220 k ? wake-up note 1: note c reg , the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 C 22 f. see figure 2-1 to select the correct esr. ? 2: c bat is the filter capacitor for the external voltage supply. 3: this diode is only needed if cs/lwake is connected to the v bat supply. 4: transient suppressor diode. 5: these components are required for additional load dump protection above 43v. 6: an external 10 k ? resistor is recommended for some applications. ( 3 ) r tp ( 5 ) 100 nf ( 6 ) v ss 220 pf mmbz27v ( 4 ) downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 15 mcp2021/2/1p/2p figure 1-7: typical mcp2022/mcp2022p application figure 1-8: typical li n network configuration lin bus v bb l bus v reg t xd rxd v ss v dd t xd rxd +12 c bat c reg cs/lwake i/o fault/ t xe i/o 43v ( 5 ) 1k ? +12 master node only +12 220 k ? wake-up note 1: note c reg , the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0 C 22 f. see figure 2-1 to select the correct esr. 2: c f is the filter capacitor for the external voltage supply. 3: this diode is only needed if is connected to the v bat supply. 4: transient suppressor diode. 5: these components are required for additional load dump protection above 43v. 6: required if cpu does not have internal pull-up. ( 3 ) r tp ( 5 ) 100 nf int or mclr reset v dd ( 6 ) v ss 220 pf mmbz27v ( 4 ) lin bus mcp202x master (mcu) 1k ? v bb slave 1 (mcu) slave 2 (mcu) slave n <16 (mcu) 40m + return lin bus lin bus mcp202x lin bus mcp202x lin bus mcp202x downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 16 ? 2005-2014 microchip technology inc. 1.6 internal voltage regulator 1.6.1 5.0v regulator the mcp2021 has a low-drop-out voltage, positive regulator capable of supplying 5.00 v dc 3% at up to 50 ma of load current, over the entire operating temperature range of -40c to +125c. with a load current of 50 ma, the minimum input to output voltage differential required for the output to remain in regulation is typically +0.5v (+1v maximum over the full operating temperature range). quiescent current is less than 100 a with a full 50 ma load current when the input to output voltage differential is greater than +3.00v. designed for automotive applications, the regulator will protect itself from double-battery jumps and up to +43v load dump transients. the voltage regulator has both short-circuit and thermal-shut-down protection built in. regarding the correlation between v bb , v reg and i dd , please refer to figure 1-10 and figure 1-11 . when the input voltage (v bb ) drops below the differential needed to provide stable regulation, the output v reg will track the input down to approximately 3.5v, at which point the regulator will turn off. this will allow microcontrol- lers with internal por circuits to generate a clean arm- ing of the por trip point. the mcp2021 will then monitor v bb and turn on the regulator when v bb rises above 5.75, again. when the input voltage (v bb ) drops below the differen- tial needed to provide stable regulation, the output v reg ) will track the input down to approximately +4.25v. the regulator will turn off the output at this point. this will allow pic microcontrollers with internal por circuits to generate a clean arming of the por trip point. the regulator output will stay off until v bb is above +5.75 v dc . in the start phase, the device must detect at least 5.75v to initiate operation during power-up. in the power-down mode, the v bb monitor will be turned off. the regulator has a thermal shutdown. if the thermal protection circuit detects an overtemperature condition, and the signals t xd and r xd are low, or t xd is high, the regulator will shut down. the recovery from the thermal shutdown is equal to adequate cooling time. the regulator requires an external output bypass capacitor for stability. see figure 2-1 for correct capacity and esr for stable operation. in worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and tem- perature. therefore, in order to ensure stability, ceramic capacitors smaller than 10 f may require a small series resistance to meet the esr requirements, as shown in tab l e 1 - 4 . table 1-4: recommended series resistance for ceramic capacitors note: the regulator has an overload current limiting of approximately 100 ma. during a short circuit, the v reg is monitored. if v reg is lower than 3.5v, the v reg will turn off. after a recovery time of about three milliseconds, the v reg will be checked again. if there is no short circuit (v reg >3.5v), the v reg will be switched back on. note: a ceramic capacitor of at least 10 f or a tantalum capacitor of at least 2.2 f is recommended for stability. resistance capacitor ? 1 f 0.47 ? 2.2 f 0.22 ? 4.7 f 0.1 ? 6.9 f downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 17 mcp2021/2/1p/2p figure 1-9: voltage regulator block diagram pass element sampling network buffer v reg v bb v ss fast transient loop v ref downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 18 ? 2005-2014 microchip technology inc. 1.6.2 3.3v regulator a metal option provides for a alternate 3.30 v dc 3% at up to 50 ma of load current over the entire operating temperature range of -40c to +125c. all specifications given above for the 5.0v operation apply except for any difference noted here. the same input tracking of 4.25v applies the 3.3v regulator. figure 1-10: voltage regu lator output on por note: the regulator has an overload current limiting of approximately 100 ma. if v reg is lower than 2.5v, the v reg will turn off. note 1: start-up, v bb mcp2021/2/1p/2p ds20002018h-page 20 ? 2005-2014 microchip technology inc. notes: downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 21 mcp2021/2/1p/2p 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on r xd and t xd .......................................................................................................... -0.3 to v reg +0.3v v in dc voltage on fault and reset .........................................................................................................-0.3 to +5.5v v in dc voltage on cs/lwake........................................................................................................ ...............-0.3 to +43v v bb battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s) .....................................-0.3 to +43 v v bb battery voltage, transient iso 7637 test 1 ................................................................................... ...................-200v v bb battery voltage, transient iso 7637 test 2a .................................................................................. .................+150v v bb battery voltage, transient iso 7637 test 3a .................................................................................. ..................-300v v bb battery voltage, transient iso 7637 test 3b .................................................................................. .................+200v v bb battery voltage, continuous ................................................................................................... .................-0.3 to +30v v lbus bus voltage, continuous....................................................................................................... ................-18 to +30v v lbus bus voltage, transient ( note 1 )............................................................................................................-27 to +43v i lbus bus short circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bb (iec 61000-4-2, 330 ohm, 150 pf) ( note 3 ) .............................................. minimum 9 kv esd protection on lin, v bb (charge device model) ( note 2 )..............................................................................1500v esd protection on lin, vbb (human body model, 1 kohm, 100 pf) ( note 4 ) ....................................................... 8 kv esd protection on lin, v bb (machine model) ( note 2 ) ..........................................................................................800v esd protection on all other pins (human body model) ( note 2 ) ............................................................................ > 4 kv maximum junction temperature ................................................................................................... .......................... 150 ? c storage temperature .................................................................................................................................. -55 to +150 ? c note 1: iso 7637/1 load dump compliant (t < 500 ms). 2: according to jesd22-a114-b. 3: according to ibee, without bus filter. 4: limited by test equipment. ? notice : stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extend ed periods may affect device reliability. downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 22 ? 2005-2014 microchip technology inc. 2.2 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions power v bb quiescent operating current i bbq 115 210 a i out = 0 ma, l bus recessive 120 215 a v out = 3.3v v bb transmitter-off current i bbto 9 01 9 0 a w i t h v reg on, transmitter off, receiver on, fault /t xe = v il , cs = v ih 9 52 1 0 a v out = 3.3v v bb power-down current i bbpd 1 62 6 a w i t h v reg powered-off, receiver on and transmitter off, fault /t xe = v ih , t xd = v ih , cs = v il ) v bb current with v ss floating i bbnognd -1 1m a v bb = 12v, gnd to v bb , v lin = 0-18v microcontroller interface high-level input voltage (t xd , fault /t xe ) v ih 2.0 or (0.25 v reg + 0.8) v reg +0.3 v low-level input voltage (t xd , fault /t xe ) v il -0.3 0.15 v reg v high-level input current (t xd , fault /t xe ) i ih -2.5 a input voltage = 0.8*v reg low-level input current (t xd , fault /t xe ) i il -10 a input voltage = 0.2*v reg pull-up current on input (t xd ) i pu t xd -3.0 a ~800 k ? internal pull-up to v reg @ v ih = 0.7*v reg high-level input voltage (cs/lwake) v ih 0.7 v reg v bb v through a current-limiting resistor low-level input voltage (cs/lwake) v il -0.3 0.3v reg v high-level input current (cs/lwake) i ih 7.0 a input voltage = 0.8*v reg low-level input current (cs/lwake) i il 3.0 a input voltage = 0.2*v reg pull-down current on input (cs/lwake) i pdcs 6.0 a ~1.3 m ? internal pull-down to v ss @ v ih = 3.5v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bb ). 2: characterized, not 100% tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 23 mcp2021/2/1p/2p bus interface high-level input voltage v ih (l bus )0 . 6 v bb 18 v recessive state low-level input voltage v il (l bus )- 8 0.4 v bb v dominant state input hysteresis v hys 0.175 v bb vv ih (l bus ) - v il (l bus ) low-level output current i ol (l bus )4 0 200 ma output voltage = 0.1 v bb , v bb = 12v pull-up current on input i pu (l bus )5 180 a ~30 k ? internal pull-up @ v ih (l bus ) = 0.7 v bb short circuit current limit i sc 50 200 ma ( note 1 ) high-level output voltage v oh (l bus )0 . 8 v bb v bb vv oh (l bus ) must be at least 0.8 v bb low-level output voltage v ollo (l bus ) 0.2 v bb v input leakage current (at the receiver during dominant bus level) i bus _ pas _ dom -1 m a d r i v e r o f f , v bus = 0v, v bat = 12v leakage current (disconnected from ground) i bus _ no _ gnd -1 +1 ma gnd device = v bat , 0v < v bus < 18v, v bat = 12v leakage current (disconnected from v bat ) i bus 10 a v bat = gnd, 0 < v bus < 18v, t a = -40 c to +85 c ( note 3 ) 50 a t a = +85 c to +125 c receiver center voltage v bus _ cnt 0.475 v bb 0.5 v bb 0.525 v bb vv bus _ cnt = (v il (l bus ) + v ih (l bus ))/2 slave termination rslave 20 30 47 k ? voltage regulator ? 5.0v output voltage v out 4.85 5.00 5.15 v 0 ma < i out < 50 ma, load regulation ? v out 2 10 50 mv 5 ma < i out < 50 ma refer to section 1.6 ?internal voltage regulator? quiescent current i vrq 2 5 a i out = 0 ma, ( note 2 ) power supply ripple reject psrr 50 db 1 v pp @10-20 khz c load = 10 f, i load = 50 ma 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bb ). 2: characterized, not 100% tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 24 ? 2005-2014 microchip technology inc. output noise voltage en 100 v rms 10 hz C 40 mhz c filter = 10 f, c bp = 0.1 f, c load 10 f, i load = 50 ma shutdown voltage v sd 3.5 4.0 v see figure 1-11 ( note 2 ) input voltage to maintain regulation v bb 6.0 18.0 v input voltage to turn off output v off 4.0 4.5 v input voltage to turn on output v on 5.5 6.0 v voltage regulator ? 3.3v output voltage v out 3.20 3.30 3.40 v 0 ma < i out < 50 ma line regulation ? v out 1 10 50 mv i out = 1 ma, 6.0v < v bb < 18v load regulation ? v out 2 10 50 mv 5 ma < i out < 50 ma refer to section 1.6 ?internal voltage regulator? quiescent current i vrq 2 5 a i out = 0 ma, ( note 2 ) power supply ripple reject psrr 50 db 1 v pp @10-20 khz c load = 10 f, i load = 50 ma output noise voltage en 100 v rms / ? hz 10 hz C 40 mhz c filter = 10 f, c bp = 0.1 f c load = 10 f, i load = 50 ma shutdown voltage v sd 2.5 2.7 v see figure 1-11 ( note 2 ) input voltage to maintain regulation v bb 6.0 18.0 v input voltage to turn off output v off 4.0 4.5 v input voltage to turn on output v on 5.5 6.0 v 2.2 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , tx = 0.4 v reg , v lbus = v bb ). 2: characterized, not 100% tested. 3: node has to sustain the current that can flow under this condition; bus must be operational under this condition. downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 25 mcp2021/2/1p/2p figure 2-1: esr curves fo r load capacitor selection load capacitor [uf] esr curves esr [ohm] 10 1 0.1 0.01 0.001 10 100 1000 1 0.1 instable instable instable stable only with tantalum or electrolytic cap. stable with tantalum, electrolytic and ceramic cap. load capacitance [f] note: the graph shows the minimum required capacitance after derating due to tolerance, temperature and voltage. unstable unstable unstable downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 26 ? 2005-2014 microchip technology inc. 2.3 ac specification ac characteristics v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym. min. typ. max. units test conditions bus interface ? constant slope time parameters slope rising and falling edges t slope 3.5 22.5 s 7.3v <= v bb <= 18v propagation delay of transmitter t transpd 4 . 0 s t transpd = max (t transpdr or t transpdf ) propagation delay of receiver t recpd 6 . 0 s t recpd = max (t recpdr or t recpdf ) symmetry of propagation delay of receiver rising edge w.r.t. falling edge t recsym -2.0 2.0 s t recsym = max (t recpdf - t recpdr ) symmetry of propagation delay of transmitter rising edge w.r.t. falling edge t transsym -2.0 2.0 s t transsym = max (t transpdf - t transpdr ) time to sample of fault / t xe for bus conflict reporting t fault 3 2 . 5 s t fault = max (t transpd + t slope + t recpd ) duty cycle 1 @20.0 kbit/sec 39.6 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? |10 nf; 500 ? th rec ( max ) = 0.744 x v bb , th dom ( max ) = 0.581 x v bb , v bb =7.0v - 18v; t bit = 50 s. d1 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 2 @20.0 kbit/sec 58.1 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? |10 nf; 500 ? th rec ( max ) = 0.284 x v bb , th dom ( max ) = 0.422 x v bb , v bb =7.6v - 18v; t bit = 50 s. d2 = t bus _ rec ( max ) / 2 x t bit ) duty cycle 3 @10.4 kbit/sec 41.7 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? |10 nf; 500 ? th rec ( max ) = 0.778 x v bb , th dom ( max ) = 0.616 x v bb , v bb =7.0v - 18v; t bit = 96 s. d3 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 4 @10.4 kbit/sec 59.0 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? |10 nf; 500 ? th rec ( max ) = 0.251 x v bb , th dom ( max ) = 0.389 x v bb , v bb =7.6v - 18v; t bit = 96 s. d4 = t bus _ rec ( max ) / 2 x t bit ) note 1: time depends on external capacitance and load. test condition: creg=4.7 f, no resistive load . 2: characterized, not 100% tested. downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 27 mcp2021/2/1p/2p 2.4 thermal specifications ( note 1 ) voltage regulator bus activity debounce time t bdb 5 10 20 s bus debounce time bus activity to voltage regulator enabled t bactve 100 250 500 s after bus debounce time voltage regulator enabled to ready t vevr 1200 s ( note 1 ) chip select to operation ready t csr 500 s chip select to power-down t cspd 8 0 s ( note 2 ) short-circuit to shut-down t shutdown 20 100 s reset timing v reg ok detect to reset inactive t rpu 1 0 . 0 s v reg ok detect to reset active t rpd 1 0 . 0 s thermal characteristics parameter symbol typ. max. units test conditions recovery temperature ? recovery +140 ? c shutdown temperature ? shutdown +150 ? c short circuit recovery time t therm 1.5 5.0 ms thermal package resistances thermal resistance, 4x4 8l-dfn ? ja 48 ? c/w thermal resistance, 8l-pdip ? ja 89.3 ? c/w thermal resistance, 8l-soic ? ja 149.5 ? c/w thermal resistance, 14l-pdip ? ja 70 ? c/w thermal resistance, 14l-soic ? ja 90.8 ? c/w thermal resistance, 14l-tssop ? ja 100 ? c/w note 1: the maximum power dissipation is a function of t jmax , ? ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ?? ja . if this dissipation is exceeded, the die temperature will rise above 150 ? c and the mcp2021 will go into thermal shutdown. 2.3 ac specification (continued) ac characteristics v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym. min. typ. max. units test conditions note 1: time depends on external capacitance and load. test condition: creg=4.7 f, no resistive load . 2: characterized, not 100% tested. downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 28 ? 2005-2014 microchip technology inc. 2.5 typical performance curves note: unless otherwise indicated, v bb = 6.0v to 18.0v; t a = -40c to +125c. figure 2-2: typical i bbq vs. temperature. figure 2-3: typical i bbto vs temperature. figure 2-4: typical i bbpd vs. temperature. figure 2-5: mcp2021-500 safe operating range. figure 2-6: mcp2021-330 safe operating range. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 0.05 0.1 0.15 0.2 -40c 25c 85c 125c i bbq (ma) temperature (c) v bb = 6v v bb = 7.3v v bb = 12v v bb = 14.4v v bb = 18v 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 -40c 25c 85c 125c ma temperature (c) v bb = 6v v bb = 7.3v v bb = 12v v bb = 14.4v v bb = 18v 0 0.005 0.01 0.015 0.02 0.025 -40c 25c 85c 125c i pd (ma) temperature (c) v bb = 6v v bb = 7.3v v bb = 12v v bb = 14.4v v bb = 18v 0 10 20 30 40 50 60 -40-34 -28 -22 -16 -10 -4 28 1420 26 32 38 44 50 56 62 68 74 80 86 92 98 104110 116 122 voltage regulator load (ma) temperature ( c) 18v dfn 18v soic 12v soic 12v dfn 0 10 20 30 40 50 60 -40-34 -28 -22 -16 -10 -4 28 1420 26 32 38 44 50 56 62 68 74 80 86 92 98 104110 116 122 voltage regulator load (ma) temperature ( c) 18v dfn 18v soic 12v soic 12v dfn downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 29 mcp2021/2/1p/2p 2.6 timing diagrams and specifications figure 2-7: bus timing diagram figure 2-8: regulator bus wake timing diagram 0.95v lbus 0.4v bb t transpdr t recpdr t transpdf t recpdf t xd l bus r xd internal t xd /r xd compare fault sampling t fault t fault fault /t xe output stable stable stable match match match match match hold value hold value 50% 50% 0.50v bb 50% 50% 0.0v v out l bus 0.4v bb t vevr v reg t bdb + t bactve downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 30 ? 2005-2014 microchip technology inc. figure 2-9: reset timing diagram figure 2-10: cs/lwake to reset timing diagram reset v bb 6.0v v reg 5.0v 5.0v 4.0v 3.5v t rpu t rpd t rpd t rp u t cspd t csr cs/lwake v reg v reg - nom reset t rpu t vevr t rpd downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 31 mcp2021/2/1p/2p 3.0 packaging information 3.1 package marking information 8-lead dfn (4x4x0.9 mm) (mcp2021, mcp2021p) example yyww nnn xxxxxx xxxxxx pin 1 pin 1 202150 e/md ^^ 1426 256 3 e or 2021p3 e/md ^^ 1426 256 3 e 8-lead dfn-s (6x5x0.9 mm) (mcp2021) example 2021330 e/mf ^^ 1426 256 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 32 ? 2005-2014 microchip technology inc. 8-lead soic (150 mil) (mcp2021, mcp2021p) example nnn 14-lead pdip (300 mil) (mcp2022) example 2021500e sn ^^1426 256 3 e mcp2022-500 e/p ^^ 1426256 3 e xxxxxxxxxxxxxnnn yyww 8-lead pdip (150 mil) (mcp2021) example 2021330 e/p ^^256 1426 3 e or 2021p33e sn ^^1426 256 3 e downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 33 mcp2021/2/1p/2p 14-lead tssop (4.4 mm) (mcp2022, mcp2022p) example yyww nnn xxxxxxxx 2022500e 1426 256 14-lead soic (150 mil) (mcp2022, mcp2022p) example mcp2022-500 e/sl ^^ 1426256 3 e or 2022p-330 e/sl ^^ 1426256 3 e or 2022p33e 1426 256 downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 34 ? 2005-2014 microchip technology inc. 8-lead plastic dual flat, no lead package (md) ? 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technolog drawing c04-131e sheet 1 of 2 downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 35 mcp2021/2/1p/2p 8-lead plastic dual flat, no lead package (md) ? 4x4x0.9 mm body [dfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technolog drawing c04-131e sheet 2 of 2 downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 36 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 37 mcp2021/2/1p/2p 8-lead plastic dual flat, no lead package (mf) 6x5 mm body [dfn-s] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. package may have one or more exposed tie bars at ends. 3. package is saw singulated. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a 0.80 0.85 1.00 standoff a1 0.00 0.01 0.05 contact thickness a3 0.20 ref overall length d 5.00 bsc overall width e 6.00 bsc exposed pad length d2 3.90 4.00 4.10 exposed pad width e2 2.20 2.30 2.40 contact width b 0.35 0.40 0.48 contact length l 0.50 0.60 0.75 contact-to-exposed pad k 0.20 note 2 a1 a a3 note 1 12 e n d exposed pad note 1 2 1 e2 l n b k b otto m view to view d2 microchip technology drawing c04-122b downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 38 ? 2005-2014 microchip technology inc. downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 39 mcp2021/2/1p/2p b a for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing no. c04-018d sheet 1 of 2 8-lead plastic dual i n-line (p) - 300 mil body [pd i p] eb e a a1 a2 l 8x b 8x b1 d e1 c c plan e .010 c 12 n note 1 top view end view side view e downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 40 ? 2005-2014 microchip technology inc. microchip technology drawing no. c04-018d sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 8-lead plastic dual i n-line (p) - 300 mil body [pd i p] units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a - - .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb - - .430 bsc: basic dimension. theoretically exact value shown without tolerances. 3. 1. protrusions shall not exceed .010" per side. 2.4. noes: -- dimensions d and e1 do not include mold flash or protrusions. mold flash or pin 1 visual index feature may vary, but must be located within the hatched area. significant characteristic dimensioning and tolerancing per asme y14.5m e datum a datum a e b e 2 b e 2 alternate lead design (vendor dependent) downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 41 mcp2021/2/1p/2p note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 42 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 43 mcp2021/2/1p/2p downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 44 ? 2005-2014 microchip technology inc. 14-lead plastic dual i n-line (p) 300 mil body [pd i p] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .735 .750 .775 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb .430 n e1 d note 1 12 3 e c b a2 l a a1 b1 b microchip technology drawing c04-005b downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 45 mcp2021/2/1p/2p note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 46 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 47 mcp2021/2/1p/2p downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 48 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 49 mcp2021/2/1p/2p note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// mcp2021/2/1p/2p ds20002018h-page 50 ? 2005-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 51 mcp2021/2/1p/2p appendix a: revision history revision h (july 2014) the following is the list of modifications: 1. updated table 1-1 . 2. updated section 1.4, pin descriptions and section 1.6.1 ?5.0v regulator? . 3. updated figures 1-6 and 1-7 . 4. updated figures 1-10 and 1-11 . 5. added section 2.5, typical performance curves . 6. updated section 3.0, packaging information . 7. updated the product identification system section. 8. minor typographical changes. revision g (july 2013) the following has been modified: 1. added note 2 in section 2.3 ?ac specifica- tion? . 2. added pull up to nfault/t xe pin in section 1.4 ?pin descriptions? and section 1.5 ?typical applications? . revision f (january 2012) the following has been modified: 1. added the mcp2021p and mcp2022p options and related information throughout the document. revision e (february 2009) the following is the list of modifications: 1. added example 1-7 and example 1-8. 2. updated section 1.4.10 ?reset? . 3. updated section 1.7 ?icsp? consider- ations? . 4. updated section 2.1 ?absolute maximum ratings?? . 5. updated section 2.2 ?dc specifications? and section 2.3 ?ac specification? . 6. added figure 2-1 in section 2.0 ?electrical characteristics? 7. updated the product identification system section. revision d (july 2008) the following is the list of modifications: 1. updated esd specs under absolute dc. 2. updated notes in example 1-1. 3. updated package outline drawings. revision c (april 2008) the following is the list of modifications: 1. added lin2.1 and j2602 compliance statement to features section. 2. added recommended rc network for cs/ lwake in example 1-1 . 3. updated 2.1 ?absolute maximum ratings?? to reflect current test results. 4. updated 2.2 ?dc specifications? and 2.3 ?ac specification? 2.3 ac specifications to reflect current production device. 5. added 8-lead soic landing pattern outline drawing. revision b (august 2007) the following is the list of modifications: 1. modified block diagram on page 2. 2. section 1.3.5 ?transmitter-off mode? : deleted text in 1st paragraph. 3. example 1-6 : removed +5v notation. 4. section 1.4 ?pin descriptions? : removed 10- pin dfn, msop column from table. 5. section 1.4.9 ?fault/txe? : deleted text from 2nd paragraph. 6. section 3.0 ?packaging information? : added 8-lead 4x4 and 6x5 dfn and 14-lead tssop packages. updated package outline drawings and added drawings for 8-lead dfn and 14-lead tssop drawings. revision a (november 2005) original release of this document. downloaded from: http:/// ds20002018h-page 52 ? 2005-2014 microchip technology inc. mcp2021/2/1p/2p product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp2021: lin transceiver with voltage regulator; wakes up on dominant level of lin bus. mcp2021t: lin transceiver with voltage regulator; wakes up on dominant level of lin bus. (tape and reel) (soic only) mcp2022: lin transceiver with voltage regulator, and reset pin; wakes up on dominant level of lin bus. mcp2022t: lin transceiver with voltage regulator, and reset pin; wakes up on dominant level of lin bus. (tape and reel) (soic only) mcp2021p: lin transceiver with voltage regulator; wakes up at a falling edge of lin bus level. mcp2021pt: lin transceiver with voltage regulator; wakes up at a falling edge of lin bus level (tape and reel) (soic only) mcp2022p: lin transceiver with voltage regulator, and reset pin; wakes up at a falling edge of lin bus level. mcp2022pt: lin transceiver with voltage regulator, and reset pin; wakes up at a falling edge of lin bus level. (tape and reel) (soic only) voltage: 330 = 3.3v 500 = 5.0v temperature range: e = -40c to +125c (extended) package: md = 8-lead plastic dual flat, no lead C 4x4x0.9 mm body (dfn) mf = 8-lead plastic dual flat, no lead C 6x5 mm body (dfn-s) p = 14-lead plastic dual in line C 300 mil body (pdip) sn = 8-lead plastic small outline C narrow, 3.90 mm body (soic) sl = 14-lead plastic small outline C narrow, 3.90 mm body (soic) st = 14-lead plastic thin shrink small outline C narrow, 4.4 mm (tssop) part no. x /xx package temperature range device examples: a) mcp2021-500e/md: 5.0v, extended temperature, 8l-dfn package. b) mcp2021t-500e/md: tape and reel, 5.0v, extended temperature, 8l-dfn package. c) mcp2021-500e/mf: 5.0v, extended temperature, 8l-dfn-s package. d) mcp2021-330e/p: 3.3v, extended temperature, 8l-pdip package. e) mcp2021-500e/p: 5.0v, extended temperature, 8l-pdip package. f) mcp2021-330e/sn: 3.3v, extended temperature, 8l-soic package g) mcp2021t-330e/sn: tape and reel, 3.3v, extended temperature, 8l-soic package. h) mcp2021-500e/sn: 5.0v, extended temperature, 8l-soic package. i) mcp2021t-500e/sn: tape and reel, 5.0v, extended temperature, 8l-soic package. a) mcp2022-330e/p: 3.3v, extended temperature, 14l-pdip package. b) mcp2022-500e/p: 5.0v, extended temperature, 14l-pdip package. c) mcp2022-330e/sl: 3.3v, extended temperature, 14l-soic package. d) mcp2022t-330e/sl: tape and reel, 3.3v, extended temperature, 14l-soic package. e) mcp2022-500e/sl: 5.0v, extended temperature, 14l-soic package. f) mcp2022t-500e/sl: tape and reel, 5.0v, extended temperature, 14l-soic package. g) mcp2022t-500e/st: tape and reel, 5.0v, extended temperature, 14l-tssop package. ?x xx voltage downloaded from: http:/// ? 2005-2014 microchip technology inc. ds20002018h-page 53 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2005-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-401-0 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ds20002018h-page 54 ? 2005-2014 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7830 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 germany - pforzheim tel: 49-7231-424750 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 03/25/14 downloaded from: http:/// |
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